Design 4 bit ripple counter using RS flip flops?

As you can see below there is something common between JK and SR flipflop i.e

The JK flip-flop augments the behavior of the SR flip-flop by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop or a T flip-flop. NOTE: The flip flop is positive edge triggered (Clock Pulse) as seen in the timing diagram.

even in the picture they Put SR/RS embeded, that mens JK can work like SR too. I will use this diagram to draw ripple counter. You may note similarity in input output combination too...

RS table

• We can summarize the operation of the RS-flipflop by the following truth table.
  R S Q Q' Comment 0 0 Q Q' Hold state 0 1 1 0 Set 1 0 0 1 Reset 1 1 ? ? Avoid

Jktable

and the corresponding truth table is:

J K Q_next Comment 0 0 hold state 0 1 reset 1 0 set 1 1 toggle

Does that mean we use below coutner 'using 4 bit ripple counter using JK flip flops' as 4 bit ripple counter for RS flip flop too? at the max output states would differ only when both SR/JK is 1 1 ?

Figure 1. A Simple Ripple Counter Consisting of J-K Flip-flops