How does core memory work?

Answer 1

Core memory is comprised of many (many) tiny toroidal (doughnet) shaped rings of ferromagnetic material. Each ring is magnetized in one direction or the other, so each ring represents one bit of information.

There are at least two wires going through each ring, a write wire and a sense wire. (More about that in a bit.) To write the ring, you create a current pulse on the write wire in one direction or the other. To read the ring, you need to write it. When you write it, if it changed state, there will be a pulse on the sense wire that you can detect. If it did not change state, there will be no sense pulse. Of course, since you wrote it, and you probably did not intend to change it, any sensed change must be followed by a rewrite to set the ring back to its original state.

Back to the write and sense wires. Having two wires for each ring is a lot of wires and a lot of electronics, particularly if you want a lot of memory, i.e. a lot of rings.

It turns out that the ring requires a certain minimum energy to change state. If you pulse too little current, nothing happens. Core memory designers use this behavior to reduce the number of wires required.

The rings are arranged in matrices, and two write wires pass through each ring. The wires are arranged in an X-Y pattern so that the intersection of a pair of wires represents only one ring. The write pulse is somewhat more than half the minumum current required to change state, but not enough on its own to change state. All of the rings on one X wire or Y wire "see" the pulse, but only the ring that "sees" both pulses actually changes state. Using this technique with 64 wires in each axis, for instance, you can control 64 times 64 or 4,096 rings with only 128 wires and pulse drivers.

Now the interesting part. The third wire, the sense wire, is threaded through all of the rings in one matrix. In this example, it would be threaded through all 4,096 rings. It can sense if any one of the rings changes state and, since only one ring is told to change state on any one cycle, we know which ring changed state.

This configuration is then repeated for the number of bits in the word so, for instance, in a 16 bit word, you would have 16 arrays. Depending on the design, the pulse drivers can actually be shared between matrices, because all of the matrices are actually operating in parallel.