How many number of machine cycles are there in each of the instructions in 8085?

Answer 1

There are following machine cycles of Intel 8085:Input-Output (I/O) Read Machine Cycle:The I/O Read Machine cycle is executed by the microprocessor to read a data from an input device. It consists of 3T states. The IN Instruction uses this machine cycle during the execution. Input - Output (I/O) Write Machine CycleThe I/O write machine cycle is executed by the microprocessor to write a data byte from an output device. It consists of 3T states. The instruction, which sends the data to the output device, comes under this machine cycle.

Instruction cycle is defined, as the time required completing the execution of an instruction.

An Instruction Cycle will have one to six machine cycles.

Answer 2

Not counting wait states... Each opcode fetch requires 4 cycles, 3 to retrieve the opcode, 1 to decode it. If there is immediate data or address as part of the instruction, there will be 3 more cycles for each byte. If there is memory access as part of the instruction, there will be 3 more cycles for each byte. Some special instructions, like a 16 bit increment, require an extra cycle.

Answer 3

INSTRUCTION SET OF INTEL 8085

An Instruction is a command given to the computer to perform a specified operation on given data. The instruction set of a microprocessor is the collection of the instructions that the microprocessor is designed to execute. The instructions described here are of Intel 8085. These instructions are of Intel Corporation. They cannot be used by other microprocessor manufactures. The programmer can write a program in assembly language using these instructions. These instructions have been classified into the following groups:

1. Data Transfer Group
2. Arithmetic Group
3. Logical Group
4. Branch Control Group
5. I/O and Machine Control Group

Data Transfer Group: Instructions, which are used to transfer data from one register to another register, from memory to register or register to memory, come under this group. Examples are: MOV, MVI, LXI, LDA, STA etc. When an instruction of data transfer group is executed, data is transferred from the source to the destination without altering the contents of the source. For example, when MOV A, B is executed the content of the register B is copied into the register A, and the content of register B remains unaltered. Similarly, when LDA 2500 is executed the content of the memory location 2500 is loaded into the accumulator. But the content of the memory location 2500 remains unaltered.

Arithmetic Group: The instructions of this group perform arithmetic operations such as addition, subtraction; increment or decrement of the content of a register or memory. Examples are: ADD, SUB, INR, DAD etc.

Logical Group: The Instructions under this group perform logical operation such as AND, OR, compare, rotate etc. Examples are: ANA, XRA, ORA, CMP, and RAL etc.

Branch Control Group: This group includes the instructions for conditional and unconditional jump, subroutine call and return, and restart. Examples are: JMP, JC, JZ, CALL, CZ, RST etc.

I/O and Machine Control Group: This group includes the instructions for input/output ports, stack and machine control. Examples are: IN, OUT, PUSH, POP, and HLT etc.

Intel 8085 Instructions

1. Data Transfer Group

   a. MOV r1, r2

   (Move Data; Move the content of the one register to another).

   [r1] ß[r2].

   b. MOV r, m (Move the content of memory register). rß[M]

   c. MOV M, r. (Move the content of register to memory). Mß[r]

   d. MVI r, data. (Move immediate data to register). [r]ßdata.

   e. MVI M, data. (Move immediate data to memory). Mßdata.

   f. LXI rp, data 16. (Load register pair immediate). [rp]ßdata 16

   bits, [rh] ß8 LSBs of data.

   g. LDA addr. (Load Accumulator direct). [A]ß[addr].

   h. STA addr. (Store accumulator direct). [addr]ß[A].

   i.LHLD addr. (Load H-L pair direct). [L] ß[addr], [H] ß[addr+1].

   j. SHLD addr. (Store H-L pair direct) [addr] ß[L], [addr+1] ß[H].

   k. LDAX rp. (LOAD accumulator indirect) [A]ß[[rp]]

   l. STAX rp. (Store accumulator indirect) [[rp]]ß[A].

   m. XCHG. (Exchange the contents of H-L with D-E pair) [H-L] <-->

   [D-E].

2. Arithmetic Group

1. ADD r. (Add register to accumulator) [A] ß[A] + [r].

2. ADD M. (Add memory to accumulator) [A] ß[A] + [[H-L]].

3. ADC r. (Add register with carry to accumulator). [A]ß[A] + [r] + [CS].

4. ADC M. (Add memory with carry to accumulator) [A]ß[A] + [[H-L]] [CS].

5. ADI data (Add immediate data to accumulator) [A]ß[A] + data.

6. ACI data (Add with carry immediate data to accumulator). [A]ß[A] + data + [CS].

7. DAD rp. (Add register paid to H-L pair). [H-L]ß[H-L] + [rp].

8. SUB r. (Subtract register from accumulator). [A]ß[A] - [r].

9. SUB M. (Subtract memory from accumulator). [A]ß[A] - [[H-L]].

10. SBB r. (Subtract register from accumulator with borrow). [A]ß[A] - [r] - [CS].

11. SBB M. (Subtract memory from accumulator with borrow). [A]ß[A] - [[H-L]] - [CS].

12. SUI data. (Subtract immediate data from accumulator) [A]ß[A] - data.

13. SBI data. (Subtract immediate data from accumulator with borrow).

    [A] ß[A] - data - [CS].

    xiv. INR r (Increment register content) [r] ß[r] +1.

    xv. INR M. (Increment memory content) [[H-L]]ß[[H-L]] + 1.

1. DCR r. (Decrement register content). [r] ß[r] - 1.

2. DCR M. (Decrement memory content) [[H-L]] ß[[H-L]] - 1.

3. INX rp. (Increment register pair) [rp] ß [rp] - 1.

4. DCX rp (Decrement register pair) [rp] ß[rp] -1.

5. DAA (Decimal adjust accumulator) .

   The instruction DAA is used in the program after ADD, ADI, ACI, ADC, etc instructions. After the execution of ADD, ADC, etc instructions the result is in hexadecimal and it is placed in the accumulator. The DAA instruction operates on this result and gives the final result in the decimal system. It uses carry and auxiliary carry for decimal adjustment. 6 is added to 4 LSBs of the content of the accumulator if their value lies in between A and F or the AC flag is set to 1. Similarly, 6 is also added to 4 MSBs of the content of the accumulator if their value lies in between A and F or the CS flag is set to 1. All status flags are affected. When DAA is used data should be in decimal numbers.

1. Logical Group

1. ANA r. (AND register with accumulator) [A] ß[A] ^ [r].

2. ANA M. (AND memory with accumulator). [A] ß[A] ^ [[H-L]].

3. ANI data. (AND immediate data with accumulator) [A]ß[A] ^ data.

4. ORA r. (OR register with accumulator) [A] ß[A] v [r].

5. ORA M. (OR memory with accumulator) [A] ß[A] v [[H-L]]

6. ORI data. (OR immediate data with accumulator) [A]ß[A] v data.

7. XRA r. (EXCLUSIVE - OR register with accumulator) [A]ß[A] v [r]

8. XRA M. (EXCLUSIVE-OR memory with accumulator) [A]ß[A] v [[H-L]]

9. XRI data. (EXCLUSIVE-OR immediate data with accumulator) [A]ß

   [A] v data.

   x. CMA. (Complement the accumulator) [A]ß[A]

10. CMC. (Complement the carry status) [CS]ß[CS]

11. STC. (Set carry status) [CS] ß1.

12. CMP r. (Compare register with accumulator) [A] - [r]

13. CMP M. (Compare memory with accumulator) [A] - [[H-L]]

14. CPI data. (Compare immediate data with accumulator) [A] - data.

    The 2nd byte of the instruction is data, and it is subtracted from the content of the accumulator. The status flags are set according to the result of subtraction. But the result is discarded. The content of the accumulator remains unchanged.

15. RLC (Rotate accumulator left) [An+1] ß[An], [A0] ß[A7],

    [CS] ß[A7].

    The content of the accumulator is rotated left by one bit. The seventh bit of the accumulator is moved to carry bit as well as to the zero bit of the accumulator. Only CS flag is affected.

A7

A0

CS

Carry Status Accumulator

Schematic diagram for RLC

1. RRC. (Rotate accumulator right) [A7] ß[A0], [CS] ß[A0], [An] ß[An+1].

   The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to the seventh bit as well as to carry bit. Only CS flag is affected.

A7

A0

CS

Carry Status Accumulator

Schematic Diagram for RRC

1. RAL. (Rotate accumulator left through carry) [An+1] ß[An], [CS] ß[A7], [A0]ß[CS].

2. RAR. (Rotate accumulator right through carry) [An] ß[An+1], [CS] ß[A0], [A7]ß[CS]

1. Branch Group

1. JMP addr (label). (Unconditional jump: jump to the instruction specified by the address). [PC] ßLabel.

2. Conditional Jump addr (label): After the execution of the conditional jump instruction the program jumps to the instruction specified by the address (label) if the specified condition is fulfilled. The program proceeds further in the normal sequence if the specified condition is not fulfilled. If the condition is true and program jumps to the specified label, the execution of a conditional jump takes 3 machine cycles: 10 states. If condition is not true, only 2 machine cycles; 7 states are required for the execution of the instruction.

   1. JZ addr (label). (Jump if the result is zero)

   2. JNZ addr (label) (Jump if the result is not zero)

   3. JC addr (label). (Jump if there is a carry)

   4. JNC addr (label). (Jump if there is no carry)

   5. JP addr (label). (Jump if the result is plus)

   6. JM addr (label). (Jump if the result is minus)

   7. JPE addr (label) (Jump if even parity)

   8. JPO addr (label) (Jump if odd parity)

3. CALL addr (label) (Unconditional CALL: call the subroutine identified by the operand)

   CALL instruction is used to call a subroutine. Before the control is transferred to the subroutine, the address of the next instruction of the main program is saved in the stack. The content of the stack pointer is decremented by two to indicate the new stack top. Then the program jumps to subroutine starting at address specified by the label.

4. RET (Return from subroutine)

5. RST n (Restart) Restart is a one-word CALL instruction. The content of the program counter is saved in the stack. The program jumps to the instruction starting at restart location.

   5. Stack, I/O and Machine Control Group

1. IN port-address. (Input to accumulator from I/O port) [A]ß[Port]

2. OUT port-address (Output from accumulator to I/O port) [Port] ß[A]

3. PUSH rp (Push the content of register pair to stack)

4. PUSH PSW (PUSH Processor Status Word)

5. POP rp (Pop the content of register pair, which was saved, from the stack)

6. POP PSW (Pop Processor Status Word)

7. HLT (Halt)

8. XTHL (Exchange stack-top with H-L)

9. SPHL (Move the contents of H-L pair to stack pointer)

10. EI (Enable Interrupts)

11. DI (Disable Interrupts)

12. SIM (Set Interrupt Masks)

13. RIM (Read Interrupt Masks)

14. NOP (No Operation)

    ADDRESSING MODES

    Each instruction requires certain data on which it has to operate. There are various techniques to specify data for instructions. These techniques are called addressing modes. Intel 8085 uses the following addressing modes:

1. Direct addressing

2. Register addressing

3. Register indirect addressing

4. Immediate addressing

   Immediate Addressing

   In immediate addressing mode the operand is specified within the instruction itself, examples are:

   i. MVI A,05 { Move 05 in register A }

   ii. ADI 06 { Add 06 to the content of the accumulator }

   Note : Refer UNIT I notes for remaining addressing modes.

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Answer 4

The JC (Jump on Carry) instruction on the 8085 will use 7 T states if the jump does not occur and 10 T states if the jump does occur.