SPLD - Simple Programmable Logic Device
Also known as:
- PAL (Programmable Array Logic, Vantis)
- GAL (Generic Array Logic, Lattice)
- PLA (Programmable Logic Array)
- PLD (Programmable Logic Device)
SPLDs are the smallest and consequently the least-expensive form of programmable logic. An SPLD is typically comprised of four to 22 macrocells and can typically replace a few 7400-series TTL devices. Each of the macrocells is typically fully connected to the others in the device. Most SPLDs use either fuses or non-volatile memory cells such as EPROM, EEPROM, or FLASH to define the functionality.
CPLD - Complex Programmable Logic Device
Also known as:
- EPLD (Erasable Programmable Logic Device)
- PEEL
- EEPLD (Electrically-Erasable Programmable Logic Device)
- MAX (Multiple Array matriX, Altera)
CPLDs are similar to SPLDs except that they are significantly higher capacity. A typical CPLD is the equivalent of two to 64 SPLDs. A CPLD typically contains from tens to a few hundred macrocells. A group of eight to 16 macrocells is typically grouped together into a larger function block. The macrocells within a function block are usually fully connected. If a device contains multiple function blocks, then the function blocks are further interconnected. Not all CPLDs are fully connected between function blocks-this is vendor and family specific. Less that 100% connection between function blocks means that there is a chance that the device will not route or may have problems keeping the same pinout between design revisions.
In concept, CPLDs consist of multiple PAL-like logic blocks interconnected together via a programmable switch matrix. Typically, each logic block contains 4 to 16 macrocells, depending on the architecture.