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An instruction queue is used in the 8086 to speed up the average time it takes to process an instruction. Some instructions are faster than the bus, while some are slower. If the CPU had to wait for all of the instructions, there would be gaps of time where the CPU is doing nothing. The queue helps to eliminate that gap by prefetching instructions in the hope that they will be ready for use when the CPU gets to them.

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13y ago
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13y ago

1) in 8088 we hav 4 byte long queue.So in order to increase the speed of execution manufacturer has increased the length of queue to 6 bytes in 8086.

2) bcoz the longest instruction in instruction set is 6bytes long. hence with a six byte long queue it is possible to prefetch even longest instruction in the instruction set.

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The instruction queue of an 8086/8088 is 6 bytes because that is how Intel designed it.

Like everything else, design decisions are made to achieve a certain level of performance balanced against cost, considering the possibilities of diminishing gains over complexity. In this writer's assumption, 6 bytes was chosen as the optimum queue size given the relatively loosely coupled execution unit to bus interface unit relationship. If you really must know the true answer, ask Intel.

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Q: Why is size of instruction queue of 8086 fixed to 6 bytes?
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What is size of instruction queue of 8086?

6 bytes


What is the length of the instruction queue in 8086?

6 bytes


What is the size of the instruction queue in 8086?

In 8086 the instruction queue is 6 byte long. This is because even the longest 8086 instruction is 6 byte long. Thus it is possible to prefetch even the longest instruction in the instruction set.


What is the maximum length of an instruction in bytes for the 8086 based IBM PC?

pata nai


Which instruction in 8086 microprocessor is 6 bytes long?

mov


Describe the functions of the 8086 queue?

The 8086/8088 instruction queue is a buffer that holds opcode bytes that have been prefetched by the bus interface unit. This speeds up operations of the processor by helping to reduce fetch latency, i.e. to improve the probability that an opcode byte fetched by the processor is already available.


Why Intel kept the name 8086?

in 8086, there is instruction queue of 6 byte. It is one of the reason behind giving name. 8086 was introducing pipeline architecture.


Why 8086 has 6 byte que?

Because that's how Intel designed it. They chose a 6 byte queue in the 8086 in order to optimize speed versus latency of the execution unit versus the bus interface unit. The decision for 6 bytes, as compared to 4 or 8 or some other number was a cost tradeoff and a recognition of the average mix of instruction execution cycle times in a typical processing thread.


What is an instruction queue in 8086?

The 8086/8088 instruction queue is a buffer that holds opcode bytes that have been prefetched by the bus interface unit. This speed up operations of the processor by helping to reduce fetches latency, i.e. to improve the probability that an opcode byte fetched by the processor is already available. This works best when there is no branching, as a branch would invalidate the queue. Advanced processors attempt to "predict" the branch, making the probability even better.


What is queue status 8086?

queue of 8086 microprocessor is 6 bits


Why pipelining used in 8086?

8086 is a pipelined processor. In 8086 to speed up the execution of a program,instruction fetching and executing the instruction are overlapped each other.This is a part of pipelined technique.


How does 8086 queue speeds up processing?

The instruction prefetch queue speeds up the processing of microprocessors by attempting to have the next opcode bytes available to the execution unit before it actually needs them. This works because, statistically, there is time spent by the execution unit in executing a particular instruction; time that the bus interface unit can use to go ahead and prefetch the next opcode bytes. Sometimes, this results in a loss of time, because the execution unit may branch to some other location. Modern processors attempt to sidestep that by using branch prediction algorithms.